module dds_AM_interface
(
input clk,rst_n,
input avs_wr_n,
input [31:0]avs_datewrite,
input [1:0]avs_address,
output reg[31:0]AM_date_k,
output reg[13:0]k,
output reg[13:0]b
);
reg date_wr_n,k_wr_n,b_wr_n;
always@(avs_address)  begin
 date_wr_n<=1'b1;
 k_wr_n<=1'b1;
 b_wr_n<=1'b1;
 case(avs_address)
  2'b01:date_wr_n<=1'b0;
  2'b10:k_wr_n<=1'b0;
  2'b11:b_wr_n<=1'b0;
  default:  begin
               date_wr_n<=1'b1;
					k_wr_n<=1'b1;
					b_wr_n<=1'b1;
				end
 endcase
end
always@(posedge clk,negedge rst_n)  begin
 if(!rst_n)
  AM_date_k<=32'b0;
 else
  if((!date_wr_n)&&(!avs_wr_n))
   AM_date_k<=avs_datewrite;
end
always@(posedge clk,negedge rst_n)  begin
 if(!rst_n)
   k<=14'd0;
 else
  if((!k_wr_n)&&(!avs_wr_n))
   k<=avs_datewrite[13:0];
end
always@(posedge clk,negedge rst_n)  begin
 if(!rst_n)
   b<=14'd0;
 else
  if((!b_wr_n)&&(!avs_wr_n))
   b<=avs_datewrite[13:0];
end
endmodule






